(1) Field of the Invention
The present invention relates to processes used to fabricate semiconductor devices, and more specifically to a process used to reduce the leakage current of a capacitor dielectric layer.
(2) Description of Prior Art
The trend to micro-miniaturization, or the use of sub-micron features, have allowed the semiconductor industry to reduce the size of semiconductor chips, resulting in a greater number of semiconductor chips, obtained from a specific size, starting substrate, thus reducing the processing cost of sub-micron, semiconductor chips. However the advent of smaller semiconductor chips, with smaller areas now allowed for specific semiconductor elements, have made the use of novel designs and configurations for dynamic random access memory, (DRAM), capacitor structures, imperative. Since there is less horizontal space allotted for the DRAM, stacked capacitor, (STC), structure, usually overlying a narrow width gate structure, the storage node structures, of stacked capacitor designs, have to be fabricated using novel configurations, comprised with multiple vertical features, extending upward from a horizontal feature of the storage node structure, to realize the desired surface area, previously achieved with larger capacitor structures. This type of configuration, as disclosed by Yang et al, in U.S. Pat. No. 5,804,852, overcomes the reduced storage node surface area, via use of a storage node structure, comprised with the multiple vertical features. The increased surface area, offered by the multiple vertical features, results in the desired capacitance, and DRAM performance, however the additional processing, and complexity, used to fabricate a storage node structure, comprised with multiple vertical features, compromises the cost benefits derived via the use of smaller semiconductor chips.
This invention will describe a DRAM fabrication process in which a high dielectric constant, capacitor dielectric layer, is used to obtain the desired, increased capacitance. The use of the high dielectric constant, capacitor dielectric layer, will offer the desired, DRAM capacitance, without employing the difficult and costly processes, needed to fabricate the multiple featured, storage node structures. Tantalum oxide, (Ta.sub.2 O.sub.5), with a dielectric constant between about 15 to 30, can be used to increase the capacitance of DRAM structures, when compared to DRAM structures fabricated with silicon oxide, capacitor dielectric layers, offering a dielectric constant of only about 3.9. However to successfully use this high dielectric constant layer, leakage currents, inherent in Ta.sub.2 O.sub.5 layers, obtained via low temperature deposition procedures, have to be reduced. This invention will teach a procedure in which a nitrous oxide anneal cycle, performed in a high density plasma, results in reductions of leakage current, evolving at normal, capacitor operating voltages. Prior art, such as Kamiyama, in U.S. Pat. No. 5,352,623, describes a method of annealing a Ta.sub.2 O.sub.5 layer at a temperature between about 600 to 1000.degree. C., in nitrous oxide, while Carl et al, describe an ozone anneal treatment for the Ta.sub.2 O.sub.5 layer, at a temperature of about 400.degree. C. However none of those prior arts describe the unique low temperature anneal conditions, using an nitrous oxide ambient, in a high density plasma, needed to reduce leakage currents.